`timescale 1ns / 1ps
module rom_tb;
  reg clka;
  reg [9:0]addra;
  wire [9:0]douta;
  rom rom(
      .clka(clka),
      .addra(addra),
      .douta(douta)
    );
    initial clka = 10;
    always #10 clka = ~clka;
  
  initial begin
    addra = 100;
    #201;
    repeat(3000) begin
        addra = addra + 1'd1;
        #20;
    end
    #2000
    $stop;
  end
Endmodule